Barcelona Architecture: AMD on the Counterattack
by Anand Lal Shimpi on March 1, 2007 12:05 AM EST- Posted in
- CPUs
AMD Virtualization Improvements
The performance-related improvement to Barcelona comes in the way of speeding up virtualized address translation. In a virtualized software stack where you have multiple guest OSes running on a hypervisor there's a new form of memory address translation that must be dealt with: guest OS to hypervisor address translation, as each guest OS has its own independent memory management. According to AMD, currently this new layer of address translation is handled in software through a technique called shadow paging. What Barcelona offers is a hardware accelerated alternative to shadow paging, which AMD is calling Nested Paging.
Supposedly up to 75% of the hypervisor's time can be spent dealing with shadow pages, which AMD eliminates by teaching the hardware about both guest and host page tables. The translated addresses are cached in Barcelona's new larger TLBs to further improve performance. AMD indicates that Barcelona's support for Nested Paging requires very little to implement; simply setting a mode bit should suffice, making the change easy for software vendors to implement.
Power Management
The most recent aspect of Barcelona's design that AMD revealed is how it handles power management. Although all four cores still operate on the same power plane (same voltage), Barcelona's Northbridge now runs on a separate power plane. Barcelona's core and Northbridge voltages can vary between 0.8V - 1.4V independently of one another.
In a conventional platform architecture, the Northbridge and the CPU are already on separate power planes given that the Northbridge is external to the CPU. The benefit of this arrangement is that the two chips can power down independently of one another, so when the memory controller has little to do, it can power down until needed. With AMD's K8, this wasn't true as the Northbridge and CPU core(s) were on the same power plane. In Barcelona, they are separated to improve power efficiency.
The individual cores still share the same reference voltage, but each core has its own PLL so that they can run at different clock speeds depending on load. While voltages of all four cores have to be equal, clock speed and thus current draw can be reduced depending on load - which will amount to power savings under normal usage conditions. The implications on the desktop are particularly interesting since it's rare that most desktop workloads will keep all cores pegged at 100% utilization.
Barcelona supports up to 5 independent p-states for each core, varying only in clock speed. The p-states are completely hardware controlled, so you will not need a driver to enable support for the power management features. AMD also increased the amount of clock gating done on Barcelona compared to K8 at both the block level and logic level. AMD wouldn't give us any more detail than this, but given how long it's been since the K8's introduction we'd expect that there's a lot that can be done.
The performance efficiency enhancements to Barcelona, coupled with updated power management, further clock gating and 65nm process allow AMD's first quad core part to operate within the same thermal envelope as current Opterons.
The performance-related improvement to Barcelona comes in the way of speeding up virtualized address translation. In a virtualized software stack where you have multiple guest OSes running on a hypervisor there's a new form of memory address translation that must be dealt with: guest OS to hypervisor address translation, as each guest OS has its own independent memory management. According to AMD, currently this new layer of address translation is handled in software through a technique called shadow paging. What Barcelona offers is a hardware accelerated alternative to shadow paging, which AMD is calling Nested Paging.
Supposedly up to 75% of the hypervisor's time can be spent dealing with shadow pages, which AMD eliminates by teaching the hardware about both guest and host page tables. The translated addresses are cached in Barcelona's new larger TLBs to further improve performance. AMD indicates that Barcelona's support for Nested Paging requires very little to implement; simply setting a mode bit should suffice, making the change easy for software vendors to implement.
Power Management
The most recent aspect of Barcelona's design that AMD revealed is how it handles power management. Although all four cores still operate on the same power plane (same voltage), Barcelona's Northbridge now runs on a separate power plane. Barcelona's core and Northbridge voltages can vary between 0.8V - 1.4V independently of one another.
In a conventional platform architecture, the Northbridge and the CPU are already on separate power planes given that the Northbridge is external to the CPU. The benefit of this arrangement is that the two chips can power down independently of one another, so when the memory controller has little to do, it can power down until needed. With AMD's K8, this wasn't true as the Northbridge and CPU core(s) were on the same power plane. In Barcelona, they are separated to improve power efficiency.
The individual cores still share the same reference voltage, but each core has its own PLL so that they can run at different clock speeds depending on load. While voltages of all four cores have to be equal, clock speed and thus current draw can be reduced depending on load - which will amount to power savings under normal usage conditions. The implications on the desktop are particularly interesting since it's rare that most desktop workloads will keep all cores pegged at 100% utilization.
Barcelona supports up to 5 independent p-states for each core, varying only in clock speed. The p-states are completely hardware controlled, so you will not need a driver to enable support for the power management features. AMD also increased the amount of clock gating done on Barcelona compared to K8 at both the block level and logic level. AMD wouldn't give us any more detail than this, but given how long it's been since the K8's introduction we'd expect that there's a lot that can be done.
The performance efficiency enhancements to Barcelona, coupled with updated power management, further clock gating and 65nm process allow AMD's first quad core part to operate within the same thermal envelope as current Opterons.
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Amiteriver - Tuesday, March 27, 2007 - link
Sounds groooovyNow lets just hope they have something good to plug it into.
trisweb2 - Friday, March 16, 2007 - link
I just want to say how refreshing it is to read an article written by Anand. He is a master of the English language; he perfectly communicates and explains every technical detail and I come away with a better understanding of whatever he's talking about.Thank you, Anand, for being a good writer!
MrWizard6600 - Thursday, March 22, 2007 - link
I Agree, Outstanding.No other site I know of gives nearly as many in depth details, and while ill admit my knowlage of some of the terms is sketchy, I got through that one with a good understanding.
Sounds like AMD has something to fight Core 2 against.
I do have one criticism:
I would have loved to have heard what Intels equivilent to all of AMDs technologies would be, mind you this criticism corrects it self toward the end of the artical.
stance - Monday, March 5, 2007 - link
Remember AMD's old president and CEO Jerry Sanders with commentslike "We will see what we see" and "More bang for your buck" I
cannot wait to see duel socket motherboards with two four core
Barcelona's working their magic. reminds me of Carol shelby
when he brought the Cobra out for road test. exciting is not
the word, jaw droping performance? Don't take Richard's Statements
lightly
lordsnow - Sunday, March 4, 2007 - link
Does anyone have any idea how compatible the "Barcelona" CPU will be with current motherboards? When it comes out, does it need a new n-phase voltage regulator, for example?the reason I'm asking is, I want to upgrade and with the current state of affairs was going to go for a C2D CPU. But with these Barcelona CPU's due out I may stick with AMD - get a AM2 motherboard and cheap AM2 CPU and upgrade to the Barcelona CPU at a later date. But I have to be sure that whatever motherboard I buy now will be 100% Barcelona compatible.
Can anyone inform us about what the situation is in this regard?
coldpower27 - Sunday, March 4, 2007 - link
Barcelona being the server variant will be compatible with the Socket F infrastructure, while Agena will be a Socket AM2+ processor compatible with exisiting Socket AM2 infrastructure.lordsnow - Sunday, March 4, 2007 - link
Any ideas as to what kind of features a user will be missing by dropping a AM2+ "Agena" CPU into a AM2 socket? The enhanced Power Saving features, perhaps?chucky2 - Sunday, March 4, 2007 - link
I asked above and non-AnandTech folks like you and I said it would...but no one from AnandTech themselves jumped right in to give an affirmative.I asked for links from AMD's own website confirming that Agena and Kuma would work in current AM2 motherboards, and no one posted back.
Right now the AM2+ CPU's will work in current AM2 boards rumor is just that, a rumor...when AMD themselves confirm it, or a site such as AnandTech confirms it with AMD and reports on it, then I'll believe it.
Until then, it's <i>probable</i> that AM2+ will work in current AM2 motherboards...if you're willing to take the risk I say go for it, else, wait until we have an official answer one way or the other.
JMHO...
Chuck
Calin - Saturday, March 3, 2007 - link
"Intel regained the undisputed performance crown it hadn't seen ever since the debut of AMD's Athlon 64."Intel in fact lost the "undisputed performance king" title during the early lifetime of the K7 architecture. The Pentium !!! was faster at some tasks and slower at others (games) than the K7. Before that, the Pentium II was better than the K6-2 (the K6-3 had better IPC than Pentium3, but was slower in MHz)
coldpower27 - Sunday, March 4, 2007 - link
Intel had the undisputed performance crown again with the Athlon XP 3200+ vs the Pentium 4 3.0C/3.2C and higher processors.